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NXP Semiconductors
10.5 SPI interfaces
LPC1111/12/13/14
Table 14.
Dynamic characteristics of SPI pins in SPI mode
Symbol
T cy(PCLK)
T cy(clk)
Parameter
PCLK cycle time
clock cycle time
Conditions
[1]
Min
13.9
27.8
Typ
-
-
Max
-
-
Unit
ns
ns
SPI master (in SPI mode)
t DS
t DH
t v(Q)
t h(Q)
data set-up time
data hold time
data output valid time
data output hold time
in SPI mode
in SPI mode
in SPI mode
in SPI mode
[2]
[2]
[2]
[2]
15
-
-
-
-
-
-
-
T cy(clk)
0
10
0
ns
ns
ns
ns
SPI slave (in SPI mode)
t DS
t DH
t v(Q)
t h(Q)
data set-up time
data hold time
data output valid time
data output hold time
in SPI mode
in SPI mode
in SPI mode
in SPI mode
[3][4]
[3][4]
[3][4]
[3][4]
0
3 × T cy(PCLK) + 4
-
-
-
-
-
-
-
-
3 × T cy(PCLK) + 11
2 × T cy(PCLK) + 5
ns
ns
ns
ns
[1]
[2]
[3]
[4]
T cy(clk) = (SSPCLKDIV × (1 + SCR) × CPSDVSR) / f main . The clock cycle time derived from the SPI bit rate T cy(clk) is a function of the
main clock frequency f main , the SPI peripheral clock divider (SSPCLKDIV), the SPI SCR parameter (specified in the SSP0CR0 register),
and the SPI CPSDVSR parameter (specified in the SPI clock prescale register).
T amb = ? 40 ° C to 85 ° C; V DD(3V3) = 2.0 V to 3.6 V; V DD(IO) = 2.0 V to 3.6 V.
T cy(clk) = 12 × T cy(PCLK) .
T amb = 25 ° C; V DD(3V3) = 3.3 V; V DD(IO) = 3.3 V.
LPC1111_12_13_14_0
? NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 00.11 — 13 November 2009
42 of 53
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